1. Field of the Invention
This invention relates to semiconductor integrated circuits and more particularly to monolithic integrated circuits of the bipolar logic families.
2. Description of the Prior Art
In designing the architecture of circuitry on a semiconductor chip, the critical factors of power dissipation circuit type, physical layout and performance must be compromised to achieve low cost. Recently, the physical layout or architecture of the chip has begun to receive increased consideration. Once a circuit family, such as Transistor-Transistor Logic (TTL), Diode-Transistor Logic (DTL), Merged Transistor Logic (MTL), etc. has been chosen, the power dissipation is more or less fixed. The performance of the design, consisting of intracell and intercell delays, is also fixed both by the circuit family as well as the physical layout. Thus, the physical layout is the remaining factor over which the semiconductor structure or circuit designer has some control.
TTL circuits enjoy widespread use in logic chips. This family offers high performance in terms of switching speed while not requiring inordinate amounts of power. They are capable of a broad range of logic functions, are relatively insusceptible to AC noise and have good fan-in and fan-out capabilities. The circuit design limitations of the TTL circuits are relatively well understood and the fabrication of such circuits in semiconductor integrated circuit form offers few problems at the present state of the art. Work has continued on reducing the cost and improving the performance of the TTL circuit by attempting to increase the packing density of the circuits within a given chip area. The same can be said for DTL and the relatively recent MTL (I.sup.2 L) circuit families.
One such example of chip architecture, or layout, which utilizes bipolar circuits is described in the application by E. A. Cass, Ser. No. 483,463, filed June 26, 1974 now U.S. Pat. No. 3,999,214, and assigned to the same assignee as the present application. In that layout, the cells are arranged in an orthogonal array, with the cells in substantially parallel rows in both orthogonal directions. In the preferred embodiment of the Cass invention, the cells are arranged in blocks which are two cells wide in the Y direction and four cells wide in the X direction. Each cell takes up substantially the same amount of chip area and has substantially the same layout configuration as every other cell. The chip layout features a regularly-structured matrix of logic gates exhibiting a nearly equal preference for data flow progression in both horizontal and vertical directions.
The Cass invention has been successful in reducing both the number of required metallization levels for intra and intercell connections as well as the size of the cells as compared to prior art layouts. In addition, the "personalization" of the chip, i.e., the placement of the metallization wiring to define a specific circuit interconnection structure by computerized design automation, is substantially easier with the Cass layout than with previous designs. However, a significant amount of chip area is unused for active devices because of the space required by the metallized wiring on the surface of the chip.